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1 typical application features description high voltage surge stopper the lt c ? 4366 surge stopper protects loads from high voltage transients . by controlling the gate of an external n-channel mosfet , the ltc4366 regulates the output during an overvoltage transient . the load may remain operational while the overvoltage is dropped across the mosfet . placing a resistor in the return line isolates the ltc 4366 and allows it to float up with the supply ; therefore , the upper limit on the output voltage depends only on the availability of high valued resistors and mosfet ratings . an adjustable overvoltage timer prevents mosfet dam - age during the surge while an additional 9-second timer provides for mosfet cool down. a shutdown pin reduces the quiescent current to less than 14a during shutdown. after a fault the ltc4366 - 1 latches off while the ltc 4366 - 2 will auto-retry . overvoltage protected 1.5a, 28v supply overvoltage protector regulates output at 43v during transient applications n rugged floating topology n wide operating voltage range: 9v to >500v n adjustable output clamp voltage n controls n-channel mosfet n adjustable protection timer n internal 9-second cool-down timer n shutdown i q < 14a n 8-lead tsot and 3mm 2mm dfn packages n industrial, automotive and avionic surge protection n high voltage dc distribution n 28v vehicle systems l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation . all other trademarks are the property of their respective owners. patents pending. v dd out 2nf gate ixtk90n25l2 sd fb 1f 0.47f 12.4k v out 1.5a v in 28v 422k 436612 ta01a 46.4k 10 324k ltc4366-2 timer base v ss 28v 100ms/div 436612 ta01b 28v 43v clamp 250v input surge v in 100v/div v out 20v/div ltc4366 436612fe for more information www.linear.com/ltc4366
2 absolute maximum ratings supply voltage ( v dd ) ................................ C0.3 v to 10 v supply voltage ( out ) ................................. C0.3 v to 5 v input voltages fb .............................................. C0.3 v to out + 0.3 v timer ................................................... C0.3 v to 3.5 v sd .......................................................... C0.3 v to 10 v output voltages base ......................................................... C1.5 v to 4 v out C base ......................................... C0.3 v to 5.5 v gate ( note 3) ........................................ C0.3 v to 15 v gate C out ( note 3) ............................. C0.3 v to 10 v (notes 1, 2) all voltages relative to v ss , unless otherwise noted. v dd 1 sd 2 timer 3 v ss 4 8 gate 7 out 6 fb 5 base top view ts8 package 8-lead plastic tsot-23 t jmax = 150c, ja = 195c/w top view 9 ddb package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1v ss timer sd v dd base fb out gate t jmax = 150c, ja = 75c/w if v ss is soldered to pcb, ja = 135c/w if v ss is not soldered to pcb exposed pad (pin 9), pcb v ss connection optional pin configuration currents i vdd ................................................................... 10 ma i out ................................................................... 10 ma base ................................................. C300 a to 10 a sd ....................................................... C10 ma to 10 a operating ambient temperature range ( note 4) ltc 4366 c ................................................ 0 c to 70 c ltc 4366 i ............................................. C40 c to 85 c ltc 4366 h .......................................... C40 c to 125 c ltc 4366 mp ....................................... C55 c to 125 c storage temperature range .................. C65 c to 150 c lead temperature ( soldering , 10 sec ) tsot -23 package only .................................... 300 c ltc4366 436612fe for more information www.linear.com/ltc4366
3 order information lead free finish tape and reel (mini) tape and reel part marking * package description temperature range ltc4366cts8-1#trmpbf ltc4366cts8-1#trpbf ltfmc 8 -lead plastic tsot-23 0c to 70c ltc4366its8-1#trmpbf ltc4366its8-1#trpbf ltfmc 8 -lead plastic tsot-23 C40c to 85c ltc4366hts8-1#trmpbf ltc4366hts8-1#trpbf ltfmc 8 -lead plastic tsot-23 C40c to 125c ltc4366cddb-1#trmpbf ltc4366cddb-1#trpbf lfmd 8-lead (3mm 2mm) plastic dfn 0c to 70c ltc4366iddb-1#trmpbf ltc4366iddb-1#trpbf lfmd 8-lead (3mm 2mm) plastic dfn C40c to 85c ltc4366hddb-1#trmpbf ltc4366hddb- 1#trpbf lfmd 8-lead (3mm 2mm) plastic dfn C40c to 125c ltc4366cts8-2#trmpbf ltc4366cts8-2#trpbf ltfmf 8 -lead plastic tsot-23 0c to 70c ltc4366its8-2#trmpbf ltc4366its8-2#trpbf ltfmf 8 -lead plastic tsot-23 C40c to 85c ltc4366hts8-2#trmpbf ltc4366hts8-2#trpbf ltfmf 8 -lead plastic tsot-23 C40c to 125c ltc4366cddb-2#trmpbf ltc4366cddb-2#trpbf lfmg 8-lead (3mm 2mm) plastic dfn 0c to 70c ltc4366iddb-2#trmpbf ltc4366iddb-2#trpbf lfmg 8-lead (3mm 2mm) plastic dfn C40c to 85c ltc 4366hddb-2#trmpbf ltc4366hddb-2#trpbf lfmg 8-lead (3mm 2mm) plastic dfn C40c to 125c ltc4366 mpts8-1#trmpbf ltc4366 mpts8-1#trpbf ltfmc 8 -lead plastic tsot-23 C55c to 125c ltc4366 mpts8-2#trmpbf ltc4366 mpts8-2#trpbf ltfmf 8 -lead plastic tsot-23 C55c to 125c ltc4366mpddb-1#trmpbf ltc4366mpddb-1#trpbf lfmd 8-lead (3mm 2mm) plastic dfn C55c to 125c ltc4366mpddb-2#trmpbf ltc4366mpddb-2#trpbf lfmg 8-lead (3mm 2mm) plastic dfn C55c to 125c trm = 500 pieces. * temperature grades are identified by a label on the shipping container . consult ltc marketing for parts specified with wider operating temperature ranges . consult ltc marketing for information on lead based finish parts . for more information on lead free part marking , go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc4366 436612fe for more information www.linear.com/ltc4366
4 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. all voltages relative to v ss , unless otherwise noted. symbol parameter conditions min typ max units v dd regulator v z(vdd) v dd shunt regulator voltage i = 1ma l 11.5 12 12.5 v ?v z(vdd) v dd shunt regulator load regulation i = 1ma to 5ma ltc4366c/i/h ltc4366mp l l 30 30 90 130 mv mv v dd v dd supply voltage (note 3) l 4.5 v z(vdd) v i vdd(stlo) v dd pin current C start-up, gate low gate = 0v, v dd = 7v, out = 0v l 15 23 a i vdd(sthi) v dd pin current C start-up, gate high gate open , v dd = 7v, out = 0v l 9 13 a i vdd(sd) v dd pin current C shutdown v dd = 7v, out = 0v l 5 8 a out regulator v z(out) out shunt regulator voltage i = 1ma, base = 0v l 5.0 5.7 6.0 v ?v z(out) out shunt regulator load regulation i = 1ma to 5ma l 30 70 mv out out supply voltage (note 3) l 3.0 v z(out) v v uvlo1 out undervoltage lockout 1 rising ltc4366c/i/h ltc4366mp l l 2.42 2.42 2.55 2.55 2.75 2.80 v v ?v uvh1 out undervoltage lockout 1 hysteresis l 0.2 0.28 0.4 v v uvlo2 out undervoltage lockout 2 rising l 4.5 4.75 4.9 v ?v uvh2 out undervoltage lockout 2 hysteresis l 0.3 0.4 0.5 v i out(amp) out pin current C regulation amplifier on l 37 54 a i out(cp) out pin current C charge pump on l 150 220 a i out(sd) out pin current C shutdown l 3 6 a base, v ss v z(base) base shunt regulator voltage (out C base) i = C10a, out = 4.5v l 5.5 6.2 6.6 v ?v z(base) base shunt regulator load regulation i = C10 a to C80a, out = 4.5v l 125 200 mv i base base pin leakage current out = 4.5v, base = C0.5v l C0.1 C0.8 C5.5 a i vss(amp) v ss pin current C regulation amplifier on l C30 C45 C72 a i vss(cp) v ss pin current C charge pump on l C108 C160 C230 a i vss(sd) v ss pin current C shutdown l C7 C12 a gate drive ?v gate external n-channel gate drive ( gate C out) out = 4.9v, i = 0, C1a l 11.2 12 12.5 v i gate (st) gate pin current C start-up gate = out = 0v ltc4366c/i/h ltc4366mp l l C4.5 C3.2 C7.5 C7.5 C11 C11 a a i gate (cp) gate pin current C charge pump on gate = 5v, out = 4.9v l C14 C20 C28 a i gate (fd) gate pin current C fast discharge gate = 10v, out = 4.9v l 122 200 300 ma i gate ( f lt ) gate pin current C fault gate = 10v, out = 4.9v l 0.3 0.7 1.2 ma ltc4366 436612fe for more information www.linear.com/ltc4366
5 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. all voltages relative to v ss , unless otherwise noted. symbol parameter conditions min typ max units fb, sd, timer v fb(reg) 3% fb pin regulation threshold (out C fb) l 1.193 1.23 1.267 v i fb fb pin leakage current out C fb = 1.2v l 0 1 a v sd(th) sd pin threshold voltage (v dd C sd) falling l 1.0 1.5 2.3 v v sd(hyst) sd pin hysteresis ltc4366c/i/h ltc4366mp l l 147 129 280 280 530 530 mv mv i sd sd pin input pull-up current v dd C sd = 0.7v ltc4366c/i/h ltc4366mp l l C0.7 C0.5 C1.6 C1.6 C3.5 C3.5 a a v timer(h) timer pin threshold timer rising, v dd = 7v, out = v z(out) l 2.6 2.8 3.1 v i timer(up) timer pin pull-up current timer = 1v ltc4366c/i/h ltc4366mp l l C5.1 C4 C9 C9 C13 C13 a a i timer(dn) timer pin pull-down current timer = 1v ltc4366c/i/h ltc4366mp l l 0.9 0.7 1.8 1.8 2.8 2.8 a a i timer( ratio) timer pin current ratio i timer(dn) /i timer(up) l 15 20 25 % ac characteristics t dly C sd sd low to gate low filter time step v dd C sd from 0v to 3v l 420 700 1200 s t dly C fast fb low to gate low delay time step out C fb from 0v to 1.3v l 60 150 300 ns t d(cool) cool-down timer (internal) v dd = v z(vdd ) ltc4366c/i/h ltc4366mp l l 5.9 5.9 9 9 16 19 seconds seconds note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive. note 3: limits on the maximum rating is defined as whichever limit occurs first. an internal clamp limits the gate pin to a maximum of 12v above source . driving this pin to voltages beyond the clamp may damage the device. note 4: t j is calculated from the ambient temperature, t a , and power dissipation, p d , according to the formula: t j = t a + (p d ? ja ) ltc4366 436612fe for more information www.linear.com/ltc4366
6 v ss current (regulation amp on) vs temperature v dd shunt regulator vs v dd current v dd shunt regulator vs temperature v dd start-up current vs temperature (gate high) out shunt regulator vs out current out shunt regulator vs temperature i vdd (ma) 0 v z(vdd) (v) 13.0 12.5 12.0 11.5 5 436612 g01 10 15 20 temperature (c) ?50 v z(vdd) (v) 13.0 11.0 50 0 100 25 ?25 75 436612 g02 125 12.5 12.0 11.5 temperature (c) i vdd(sthi) (a) 15 12 9 6 3 436612 g03 ?50 50 0 100 25 ?25 75 125 i out (ma) v z(out) (v) 5.9 5.8 5.7 5.6 5.5 436612 g04 0 5 10 15 20 ?50 50 0 100 25 ?25 75 125 temperature (c) v z(out) (v) 7 6 5 4 436612 g05 temperature (c) i vss(amp) (a) 75 50 25 0 436612 g10 ?50 50 0 100 25 ?25 75 125 typical performance characteristics v ss current (charge pump on) vs temperature gate drive vs gate pull-up current gate current (charge pump on) vs temperature i gate(cp) (a) ?40 ?30 ?20 ?10 0 436612 g14 temperature (c) ?50 50 0 100 25 ?25 75 125 temperature (c) i vss(cp) (a) ?300 ?200 ?100 0 436612 g11 ?50 50 0 100 25 ?25 75 125 i gate (a) 0 ?v gate (v) 16 12 8 4 0 ?10 ?20 436612 g12 ?30 ltc4366 436612fe for more information www.linear.com/ltc4366
7 typical performance characteristics gate start-up current vs temperature i gate(st) (a) ?12 ?10 ?8 ?6 ?4 436612 g15 temperature (c) ?50 50 0 100 25 ?25 75 125 base shunt regulator vs base current timer pull-up current vs temperature i timer(up) (a) ?12 ?10 ?8 ?6 ?4 436612 g18 temperature (c) ?50 50 0 100 25 ?25 75 125 i base (a) 0 v z(base) (v) 7.0 6.5 6.0 5.5 ?100 436612 g16 ?200 ?300 ?400 ?500 sd pull-up current vs temperature temperature (c) i sd (a) ?3 ?2 ?1 0 436612 g21 ?50 50 0 100 25 ?25 75 125 fb regulation threshold vs temperature cool-down time vs temperature v fb(reg) (v) 1.24 1.23 1.22 1.21 436612 g22 temperature (c) ?50 50 0 100 25 ?25 75 125 temperature (c) t d(cool) (s) 16 10 12 14 6 8 436612 g23 ?50 50 0 100 25 ?25 75 125 ltc4366 436612fe for more information www.linear.com/ltc4366
8 pin functions base: base driver output for external pnp shunt regula - tor. this pin is connected to the anode of an internal 6.2v zener with the cathode tied to out. in cases where lower zener (z3) clamp current is desired but a large v ss resis - tor is prohibited , connect an external pnp base to this pin (pnp collector is grounded , emitter is tied to v ss ). tie this pin to v ss if unused. exposed pad: the exposed pad may be left open or con - nected to v ss . fb: overvoltage regulation amplifier feedback input. connect this pin to an external resistive divider from out to ground. the overvoltage regulation amplifier controls the gate of the external n-channel mosfet to regulate the fb pin voltage at 1.23v below out . the overvoltage amplifier will activate a 200 ma pull-down on the gate pin during a fast overvoltage event . gate : gate drive for external n-channel mosfet . dur - ing start-up an internal 7.5 a current source charges the gate of the external n-channel mosfet from the v dd pin. once the out voltage is above v ss by 4.75v, the charge pump will finish charging the gate to 12v above out . during a fast overvoltage event , a 200ma pull-down cur - rent source between gate and out is activated , followed by regulation of the gate pin voltage by the overvoltage regulation amplifier. out: charge pump and overvoltage regulation amplifier supply voltage . supply input for floating circuitry powered from the mosfet source . once the out voltage is 4.75v ( uvlo2) above v ss , the charge pump will turn on and draw power from this pin. when out exceeds 2.55v (uvlo1) it is used as a power supply and reference input for over - voltage regulation amplifier. this pin is clamped at 5.7 v and requires a 0.22f or greater bypass to the v ss pin. sd: shutdown comparator input . tie to v dd if unused . connect pin to a limited current pull down created by adding a resistor in series with an open-drain or open-collector pull-down transistor. activating the external pull down overcomes the internal 1.6 a pull-up current source and allows the sd pin to cross the shutdown threshold. this threshold is defined as 1.5v below v dd with a 280mv hysteresis. to prevent false triggers this pin must stay below the threshold for 700s to activate the shutdown state. the shutdown state lowers the total quiescent cur - rent (i vdd plus i out ) below 20a. this quiescent current does not include shunt current in the v dd , out and base regulators. after a fault on the ltc4366, putting the part in shutdown will clear the fault and allow operation to resume. clearing the fault during the 9 -second cool-down period will shorten the timeout for the ltc4366-2 (auto- retry ) version. timer : timer input . leave this pin open for a 1 s overvolt - age regulation period before fault off . connect a capacitor between this pin and v ss to set a 311ms/f duration for overvoltage regulation before the switch is turned off . the ltc4366-2 version will restart after a nine second cool-down period. v dd : start-up supply. supply input for 7.5 a start-up cur - rent source that charges the gate of the external n-channel mosfet. also provides supply for timer and logic circuits active when the external mosfet is off . this pin is clamped at 12 v above v ss . do not bypass this pin with a capacitor . v ss : device return and substrate . the capacitors on the timer and out pins should be returned to this pin. ltc4366 436612fe for more information www.linear.com/ltc4366
9 simplified diagram functional diagram ? + r fb1 r fb2 436612 sd r ss r ss r ss cp z1 12v 7.5a 20a z3 5.7v z3 5.7v r in 1.23v + ? + ? charge pump f = 2mhz uvlo2 4.75v m1 out fb gate out v dd sd d1 7.5a 20a overvoltage amplifier logic supply v cc out z1 12v logic and timer shutdown comparator + ? timer comparator uvlo1 2.55v z2 6.2v z3 5.7v z4 12v 2.8v v cc v cc v dd 9a timer base v ss 1.8a 1.6a c g v out c t r fb1 r g r in v in r fb2 r ss 436612 fd c1 + ? 1.5v + ? 1.23v + ? ? + start run regulate ltc4366 436612fe for more information www.linear.com/ltc4366
10 operation the simplified diagram shows three states of operation: the start , run and regulate mode. previous surge stopper parts are powered off the input supply , therefore the surge voltage is limited to the breakdown voltage of the input pins of the part. as demonstrated in run and regulate modes, the majority of this part is powered off the output , so the mosfet isolates the surge from the power pins of the part. this allows surge voltages up to the breakdown of the external mosfet. in the start mode a 15a trickle current flows through r in , half is used to charge the gate with the other half used as bias current . as the gate pin charges , the external mosfet brings up the out pin . this leads to the run mode where the output is high enough to become a supply voltage for the charge pump . the charge pump is then used to fully charge the gate 12 v above the source. with the output voltage equal to the input voltage , it is necessary to protect the load from an input supply over - voltage. in the regulate mode , the overvoltage regulation amplifier is referenced to the output through a 1.23v reference. if the voltage drop across the upper feedback resistor , r fb1 , exceeds 1.23 v the regulation amplifier pulls the gate down to regulate the r fb1 voltage back to 1.23v. therefore, the output voltage is clamped by setting the proper ratio between r fb1 and r fb2 . for example, if the output voltage is regulated at 100v then the voltage drop across the r fb2 is 98.77v. if the zener z 3 is 5.7v then the voltage drop across r ss is 94.3v. there- fore, when the output is at a high voltage , the majority of the voltage is dropped across the two resistors r fb2 and r ss . this demonstrates how the ltc4366 floats up with the supply. the adjustable 3-terminal regulators , such as the lt ? 1085 and lm117, are also based on this idea. the functional diagram shows the actual circuits . an external r in resistor on the v dd pin powers up the 12v shunt regulator which then powers up logic supply , v cc . after verifying that the shutdown input is not active , the gate pin is charged with a 7.5a current from v dd . this is the start mode. once the out to v ss voltage exceeds the 2.55v uvlo1 threshold, the overvoltage amplifier is enabled . next, the uvlo2 threshold of 4.75 v is crossed and the charge pump turns on. the charge pump charges the gate pin with 20 a to its final value 12 v above out ( clamped by z 4). this allows the capacitor between out and v ss to charge until clamped by z 3 to 5.7v. in this run mode the mosfet is configured as a low resistance pass transistor with little voltage drop and power dissipation in the mosfet. the powered up ltc4366 is now ready to protect the load against an overvoltage transient . the overvoltage regula- tion amplifier monitors the load voltage between out and ground by sensing the voltage on the fb pin with respect to the out pin (drop across r fb1 ). in an overvoltage condition the out rises until the amplifier drives the m 1 gate to regulate and limit the output voltage . this is the regulate mode. during regulation the excess voltage is dropped across the mosfet. to prevent overheating the mosfet , the ltc4366 limits the overvoltage regulation time using the timer pin . the timer pin is charged with 9a until the pin exceeds 2.8v. at that point an overvoltage fault is set , the mosfet is turned off , and the part enters a cool-down period of 9 seconds. the logic and timer block are active during cool down while the gate pin is pulled to out . the latched-off version , ltc4366-1, will remain in fault until the sd pin is toggled low and then high. once the fault is cleared, the gate is permitted to turn the mosfet on again . the auto-retry version , ltc 4366 - 2, waits 9 seconds then clears the fault and restarts. ltc4366 436612fe for more information www.linear.com/ltc4366
11 applications information the typical ltc4366 application is a protected system that distributes power to loads safe from overvoltage transients. external component selection is discussed in the following sections. dual shunt regulators the ltc4366 uses two shunt regulators coupled with the external voltage dropping resistors, r ss and r in , to generate internal supply rails at the v dd and out pins . these shunt-regulated rails allow overvoltage protection from unlimited high voltage transients irrespective of the voltage rating of the ltc4366 s internal circuitry. at the beginning of start-up , during shutdown, or after an overvoltage fault , the gate pin is clamped to the out pin thereby shutting off the mosfet. this allows the v ss and out pins to be pulled to ground by output load and r ss . under this condition the v dd pin is clamped with a 12v shunt regulator to v ss . the full supply voltage minus 12v is then impressed on the r in resistor which sets the shunt current. the shunt current can be as high as 10ma which is several orders of magnitude higher than the typical 9a v dd pin quiescent current. in normal operation the out voltage is equal to the input supply . with c 1 fully charged i c 1 is zero at this point . under this condition the voltage between the out and v ss pins are clamped with a 5.7v shunt regulator. the input supply voltage minus 5.7v is impressed on r ss . the r ss current is divided into three areas: the 5.7v shunt current, bias current between out and v ss and finally the r in current. the 5.7 v shunt current can be as high as 10 ma which greatly exceeds the typical out (160a) bias current. turn-on sequence the voltage between the v dd and v ss pins is shunt regu - lated to 12v after ramping up the input supply . next, the internally generated supply , v cc , produces a 30 s power- on-reset pulse which clears the fault latch and initializes internal latches . next , the shutdown comparator determines if the sd pin is externally pulled low, thereby requesting a low bias current shutdown state . otherwise the external mosfet, m1, is allowed to turn on. turning on the 7.5 a gate pull-up current source from the v dd pin begins what can be described as a bootstrapped method for powering up the mosfet gate . once the gate reaches the v dd pin voltage ( minus a schottky diode), the 7.5 a source loses voltage headroom and stops charging the gate ( middle of waveforms in figure 2.). the bootstrap method relies on charging c 1 to a sufficient voltage after gate stops increasing . the voltage on c1 is then used as a supply for a charge pump that charges the gate to its final value 12v above out. c1 will discharge if the charge pump current exceeds the c 1 charging current . if the voltage drops below 4.35v, the charge pump will pause allowing c1 to recharge. v dd sd r1 470k r2 100k out c g 10nf gate m1 fqa62n25c sd fb c t 8.2nf c1 0.47f r fb1 12.4k v out 1.5a (43v clamp) v in 28v (18v dc to 250v dc) r fb2 422k 436612 f01 r ss 46.4k r g 10 r in 324k q1 mmbt3904 ltc4366-2 timer base v ss figure 1. typical application figure 2. turn-on waveforms v gate 10v/div v out 10v/div v c1 5v/div 20ms/div 436612 ta01b charge pump pause charge pump starts c1 charging c1 recharging ltc4366 436612fe for more information www.linear.com/ltc4366
12 applications information starting up with a supply voltage insufficient to charge c1 with large load current may result in overheating the mosfet and subsequent damage . while the gate and output are ramping the drop across the mosfet is the input supply minus the output. if the supply is lower than necessary to charge c 1, then the output fails to ramp higher than the supply minus the threshold of the mosfet . this 3v to 5v mosfet drop with high load current will result in power dissipation without any protection or timeout limit . overvoltage fault the ltc4366 prevents an overvoltage on the input supply from reaching the load. normally, the pass transistor is fully on , powering the load with very little voltage drop. as the input voltage increases the out voltage increases until it reaches the regulation point (v reg ). from that point any further voltage increase is dropped across the mosfet . note the mosfet is still on so the ltc4366 allows un - interrupted operation during a short overvoltage event . the v reg point is configured with the two fb resistors , r fb 1 and r fb2 . the regulation amplifier compares the fb pin to a threshold 1.23 v below the out pin . during regulation the drop across r fb1 is 1.23v, while the remainder of the v reg voltage is dropped across r fb2 . when the output is at the regulation point a timer is started to prevent excessive power dissipation in the mosfet . normally the timer pin is held low with a 1.8 a pull- down current. during regulation the timer pin charges with 9a. if the regulation point is held long enough for the timer pin to reach 2.8 v then an overvoltage fault is latched. the equation for setting the timer capacitor is: c t = 3.2 ? t nf / ms [ ] depending on which version , the part will cool down and self start (ltc4366-2), or remain latched off until the sd pin activates a shutdown followed by a start-up command ( ltc 4366 - 1). the cool-down time is typically nine seconds which provides a very low pulsed power duty cycle . starting up with an input supply overvoltage and full load current does increase the power dissipation in the mosfet well beyond the case for an overvoltage surge . during the gate and output ramp up , the partial supply voltage (at full current) is dropped across the mosfet . after start-up the normal overvoltage surge (with timeout) occurs before the shutting off the mosfet . the design example section only considers the normal overvoltage surge for safe operating area (soa) calculations for the mosfet. start-up into overvoltage will require additional soa considerations. shutdown the ltc4366 has a low current (<20a) shutdown state that turns off the pass fet by tying the gate and out pins together with a switched resistor. in the normal operating condition, the sd pin is pulled up to the v dd pin voltage with a 1.6 a current source . tie the sd pin to v dd when the shutdown state is not used. bringing the sd pin more than 1.5v below v dd pin volt - age for greater than the 700s filter time activates the shutdown state. this filter time prevents unwanted activa - tion of shutdown during transients . the sd pin is diode clamped 0.7v below v ss which requires current limiting (maximum 10ma) on the pull-down device. one way to limit the current is to connect an external 470k resistor in series with the open-collector pull-down device. activat- ing the external pull-down overcomes the internal 1.6a pull-up current source and allows the sd pin to cross the shutdown threshold. ltc4366 436612fe for more information www.linear.com/ltc4366
13 applications information following an overvoltage fault , putting the part in shutdown will clear the fault, allowing operation to resume once the ltc4366 leaves shutdown. output short a sudden short on the output can result in excessive cur - rent into the ltc4366 gate pin supplied from the gate capacitor, c g . the gate pin is internally clamped to out with a 10 v to 12 v clamp. if the out pin is pulled low while the gate pin is held up with c g , then the clamp will be damaged trying to discharge c g when clamp voltage is exceeded. one solution is to add a 1k r s resistor in series with c g with a bypass diode as shown in figure 3. the diode allows the capacitor to function as a bypass for energy coming from the mosfet drain to gate capacitor during an supply overvoltage . gate d bypass r s 1k c g 436612 f03 r g m1 ltc4366 out 10v to 12v figure 3. output short protection ltc4366 base 436612 f04 r ss v ss figure 4. external pnp option resistor power ratings the proper rating for the r ss resistor in figure 1 must be considered. during an overvoltage event the out pin is at regulation voltage (v reg ), so the voltage across r ss is v reg minus 5.7v . a small minimum supply voltage reduces the value of r ss . therefore, large differences between minimum supply voltage and the regulation voltage may require a large power resistor for r ss . the full supply voltage minus 12v can appear across r in during the overvoltage cool-down period . normally the value for r in is several times larger than r ss which lowers the power and size requirements for this resistor . external pnp in some cases the power resistor for r ss may be physically large. a large value r ss (with lower power and size ) may be used in conjunction with a pnp as shown in figure ?4. in addition to the 0.8 a sourced from the base pin , the base current from the pnp must flow through r ss which will limit the maximum r ss value . in some cases the minimum pnp beta is as low as 35. the base current becomes 10a when the v ss current is 350a. one can see this allows a 35 (beta) times larger r ss than the ap - plication without the pnp. minimum supply start-up when designing for the minimum supply condition , it is important that r ss and r in are chosen to provide enough current to sufficiently charge c 1 to 4.75v. the parameters that determine the minimum supply voltage include : c1 voltage , mosfet threshold voltage , a series schottky diode voltage drop, resistance of r ss and r in , current in the v dd ltc4366 436612fe for more information www.linear.com/ltc4366
14 applications information pin, and finally the current from the v ss pin (see figure 5). v in(min) = (i vdd ? r in ) + v d + v th + v c1 + (i vss ? r ss ) using the electrical characteristics table for above parameters: v c1 = v uvlo2 = 4.75v (uvlo2 threshold) i vdd = i vdd(sthi) = 9a (i vdd start-up, gate high) i vss = i vss(amp) = 45a (i vss w/regulation amp ) v d = 0.58v v in ( min ) = (9 a ? r in ) + 0.58 v + v th + 4.75 v + (45 a ?? ? r ss ) when the mosfet gate is fully enhanced , the out pin voltage is equal to the supply voltage . this places another constraint on the minimum supply voltage because the charge pump increases the v ss current to 160a. the c 1 voltage is assumed to be clamped at 5.7v. these values are specified as v z(out) and i vss(cp) (charge pump on) in the table of electrical characteristics: v in(min) = v z(out) + (i vss(cp) ? r ss ) or v in(min) = 5.7v + (160a ? r ss ) the last v in(min) equation sets the maximum value for r ss . after choosing r ss the maximum value for r in (for that particular r ss ) is calculated from the first v in(min) equation: r ss(max) = v in(min) C 5.7v 160a r in(max) = v in(min) C 4.75v C 0.58v C v th C 45a ? r ss ( ) 9a these two equations maximize the values of r ss and r in (reducing power dissipation) while still providing the necessary v c1 voltage to turn the charge pump on . increasing the supply voltage beyond the minimum sup - ply voltage increases the current and power in r ss while reducing the time required to charge c 1. conditions that may require an even smaller r ss(max) will be discussed in the maximum supply start-up section. maximum supply start-up the maximum overvoltage supply may also exist during start-up. the overvoltage protection circuitry has to wake up before high voltage is passed to the load . dynamically the gate is ramping up while c 1 is charging. capacitor c1 must charge to the 2.55v uvlo1 threshold to turn on the regulation amplifier and reference before the out pin voltage exceeds the overvoltage regulation point , v reg . these conditions may reduce the value of r ss below the maximum value dictated by the minimum supply start-up discussed above. when current in r ss exceeds the current sourced from the v ss pin (essentially i rin ), the capacitor c1 begins to charge. the voltage at the v ss pin when i rin = i rss is now labeled v ss( match) . the v ss pin voltage is the center of a voltage divider between r in and r ss after the zener clamp voltage from v dd to v ss is subtracted from the supply. v ss(match) = r ss r ss + r in ? v in(max) C v z(vdd) ( ) as v in increases the v ss( match) voltage increases. if the match voltage exceeds the overvoltage regulation point (v reg ), then load is unprotected. this is true because c1 will still need to charge to 2.55v while v ss already m1 gate d1 7.5a c g v dd r in i rin v in z3 5.7v z1 12v i bias i shunt2 9a i shunt1 i c1 i rss v out out r load 436612 f05 r ss v ss circuits logic timer v c1 c1 + ? figure 5. simplified block diagram ltc4366 436612fe for more information www.linear.com/ltc4366
15 applications information has exceeded v reg . since the out pin voltage is at least 2.55v larger than v ss it exceeds the specified maximum . choosing the match point (with supply at the maximum ) sufficiently below v reg (by at least 2.55v), allows c1 to charge up in time to protect the load from overvoltage . in reality having v ss pin voltage 7v below v reg provides required margin for charging c1. v ss( match)(max) = v reg C 7v increasing r ss increases the match point , so determin- ing the maximum r ss value while still protecting from overvoltage is useful . using i rin = i rss : r ss = r in ? v rss v rin using: v rss = v ss( match)(max) = v reg C 7v v rin = v in C v z(vdd) C v rss substituting: r ss(max) = r in ? v reg C 7v ( ) v in(max) C 12v C v reg C 7v ( ) r ss(max) = r in ? v reg C 7v ( ) v in(max) C 5v C v reg if we guarantee that r ss < r ss(max) then the following is true: v ss( match) < v ss( match)(max) c1 bypasses the charge pump , and requires at least a 0.22f . the size of c 1 needs limits also . the gate capaci - tor (c g ) dictates the maximum output capacitor c 1 (max) that will charge to the 2.55v uvlo1 threshold (v uvlo1 ) before the out voltage exceeds the overvoltage threshold . c1 (max ) = Cc g ? r ss + r in ( ) v reg C v ss(match ) ( ) i g ? r ss ? r in ?in 1C 2 ? v uvlo1 v reg C v ss(match ) ? ? ? ? ? ? ? ? in most cases: c1 (max) = 10 ? c g to 100 ? c g gate capacitor , c g the gate capacitor is used for three functions. first, c g absorbs charge from the gate-to-drain capacitance of the mosfet during overvoltage transients . second, the capacitor also acts as a compensation element for the overvoltage regulation amplifier . the minimum value for c g to guarantee stability is 2nf. finally, c g sets the slew rate of the gate and out pins . the voltage at the gate pin rises at a slope equal to 20a/c g . this slope determines the charging current into the load capacitor. i inrush = c load c g ?i g the voltage rating for c g must be greater than the regula - tion voltage (v reg ). mosfet selection the ltc4366 drives an n-channel mosfet to conduct the load current. the important features of the mosfet are on-resistance, r ds(on) , the maximum drain-source voltage, v (br)dss , the threshold voltage, and the soa. the maximum allowable drain-source voltage must be higher than the supply voltage. if the output is shorted to ground or during an overvoltage event , the full supply voltage will appear across the mosfet. the threshold voltage of the mosfet is used in the mini - mum supply start-up calculation. for applications with supplies less than 12v, a logic-level mosfet is required . above 12v a standard threshold n-channel mosfet is sufficient. the soa of the mosfet must encompass all fault condi - tions. in normal operation the pass transistor is fully on, dissipating very little power . but during overvoltage faults , the gate pin is servoed to regulate the output voltage through the mosfet . large current and high voltage drop across the mosfet can coexist in these cases . the soa curves of the mosfet must be considered carefully along with the selection of the fault timer capacitor . ltc4366 436612fe for more information www.linear.com/ltc4366
16 applications information layout considerations due to the high impedances on the sd, v dd , and gate pins, these pins are susceptible to leakages to ground . for example , a leakage to ground on sd will activate the shutdown state if greater than 1.6a. providing adequate spacing away from grounded traces and adding conformal coating on exposed pins lowers the risk that leakage cur - rent will interrupt system operation. it is important to put the bypass capacitor, c1, as close as possible to the out and v ss pins. place the 10 resistor as close as possible to the mosfet gate pin . this will limit the parasitic trace capacitance that leads to mosfet self-oscillation. the fb pin is sensitive to parasitic capacitance when the regulation loop is closed. one result from this capacitive loading is output oscillations during overvoltage regula - tion. it is suggested that the resistors r fb1 and r fb2 be placed close to the pin and that the fb trace itself be minimized in size. design example overview the design process starts with minimum input voltage start-up equations to calculate values for r ss and r in . these values need further refinement to meet two other conditions: the maximum input voltage start-up condi - tions and proper current for the charging of c 1. the the remaining element values are calculated based on the input parameters. following are the input parameters for this example: v supply (min) = 18v, v reg = 43v, v in(max) = 250v, i load = 1.5a at start-up, i load = 3a after start-up, v th = 5v important electrical characteristics table parameters used in this example are summarized in table 1. step 1: maximum r ss in this design example (figure 6.) the component sizing first considers the start-up phase after the charge pump is active. the goal is to maximize the resistance of r ss which still allows operation when the input voltage is at the minimum value. v dd sd r1 470k r2 100k out c g 10nf gate m1 fqa62n25c sd fb c t 8.2nf c1 0.47f r fb1 12.4k v out 1.5a (43v clamp) v in 28v (18v dc to 250v dc) r fb2 422k 436612 f06 r ss 46.4k r g 10 r in 324k q1 mmbt3904 ltc4366-2 timer base v ss figure 6. overvoltage protected 28v, 1.5a supply ltc4366 436612fe for more information www.linear.com/ltc4366
17 applications information after the charge pump is active the v ss current increases to 160a (worst-case 230a, see table 1) current while the final value out voltage is equal to the minimum supply voltage. the c 1 voltage is clamped at 5.7v (worst-case 6.0v): r ss(max) = v in(min) C v z(out) i vss(cp) r ss(max) = 18v C 6v 230a = 52.3k step 2: determine r in the value for resistor r in is calculated using the calculated r ss value . r in is chosen to provide enough headroom to sufficiently charge c 1 to 4.9 v the maximum undervoltage lockout 2 threshold ( v uvlo 2 ) which starts the charge pump . the parameters that determine r in include: minimum supply voltage, the final c 1 voltage, mosfet threshold voltage, r ss , 72a maximum v ss pin current (regulation amplifier on, i vss(amp) ), and finally the 13a maximum start-up current in the v dd pin (i vdd(sthi) ): r in(max) = v in(min) C v uvlo2 ? v d ? v th ? i ss(amp) ? r ss ( ) i vdd(sthi) r in(max) = 18v ? 4.9v ? 0.58v ? 5v ? 72a ? 52.3k ( ) 13a r in(max) = 287k table 1. electrical parameters used in design example symbol parameter conditions typ max v z(out) out shunt reg. voltage i = 1ma, base = 0v 5.7v 6.0v v uvlo2 out undervoltage lockout 2 rising 4.75v 4.9v i vss(cp) v ss pin current C charge pump on C160a C230a i vss(amp) v ss pin current C regulation amplifier on C45a C72a i vdd(sthi) v dd pin current C start-up, gate high gate open , v dd = 7v, out = 0v 9a 13a i gate (st) gate pin current C start-up gate = out = 0v C7.5a C11a v uvlo1 out undervoltage lockout 1 rising 2.55v 2.75v step 3: find r ss( max) in some cases this value for r ss is too large to charge c 1 and power the overvoltage amplifier before the maximum input voltage passes to the output . the voltage at the v ss pin when i rin = i rss is called the match point (v ss( match) ). choosing the match point (with supply at the maximum ) sufficiently below v reg ( by at least 7 v ), allows c 1 to charge up in time to protect the load from overvoltage : r ss(max) = r in ? v reg C 7v ( ) v in(max) ? 5v ? v reg r ss(max) = 287k ? 43v C 7v ( ) 250v C 5v C 43v = 51.1k in this case the r ss value of 52.3k calculated in step 1 is too large. step 4: iterate smaller r ss using 51.1k (r ss(max) ) as the next guess for r ss , we can now calculate r in and r ss(max) : r in = 18v C 4.9v ? 0.58v ? 5v ? 72a ? 51.1k ( ) 13a r in = 294k r ss(max) 294k ? 43v C 7v ( ) 250v C 5v ? 43v = 52.3k in this case the r ss value of 51.1k is less than r ss(max) and the solution is acceptable. ltc4366 436612fe for more information www.linear.com/ltc4366
18 step 5: determine c g , c1 (max) , check r ss the gate capacitor (c g ) determines the gate slew rate and therefore the slew rate of the out pin since the output voltage follows the gate pin . the voltage at the gate pin rises with a slope equal to 7.5 a / c g at startup and 20 a / c g when the charge pump is on . limiting this slope will limit the inrush current charging the load capacitance where: i inrush = c load c g ?i g in this example we choose c g to be 10nf which limits the inrush current to be 660ma for a 330f c load . c1 is used as a bypass capacitor for the circuitry between the out and v ss pins. c1 also stabilizes the shunt regula- tor that clamps the voltage between these pins where the minimum value for regulator stability is 0.22f. an even greater 0.47f value is desired for c 1 to protect the out to v ss circuitry from transients on the out pin . the startup into an overvoltage creates an upper bound - ary on the value of c 1. the value of c g , r ss and r vin determines a maximum c 1 that will reach uvlo 1 and power the regulation amplifier before the out pin voltage exceeds the overvoltage threshold . if our desired value for c1 (0.47f) exceeds the maximum allowed c 1 then a smaller r ss must be used to iterate a new solution for c1 (max) . we start with calculating v ss( match) : v ss(match) = r ss r ss + r vin ? v in C v z(vdd) ( ) if we use the worst-case 1% maximum value for r ss (51.6k) and minimum value for r vin (291k): v ss( match) = 35.8v c1 (max) = Cc g ? r ss + r in ( ) v reg C v ss(match) ( ) i g ? r ss ? r in ?in 1C 2 ? v uvlo1 v reg C v ss(match) ? ? ? ? ? ? ? ? use the worst-case maximum gate current of 11 a instead of the typical 7.5 a and the worst-case minimum uvlo1 applications information threshold, 2.75v: c1 (max ) = C10nf ? 51.6k + 291k ( ) 43v C 35.8v ( ) 11a ? 51.6k ? 291k ?in 1C 2 ? 2.75v 43v ? 35.8v ? ? ? ? ? ? or c1 (max) = 0.1f this limit on c1 does not meet the shunt regulator stability requirements (c1 > 0.22f). if we desire a larger value of c 1 then a lower size of r ss is required. a lower value for r ss is 48.7k, which calls out an r in value of 309k and a max c 1 value of 0.27f. the next lower value of 46.4k with r vin of 324k, results in the worst-case maximum c1 value of 0.49f. a larger c1 increases circuit immunity to transients in exchange for slightly higher current . therefore, a selection of com - ponents that allow a 0.47f c1 is recommended. the lowered r ss value of 46.4k now considers the toler - ances of all the components that set the c 1 ramp rate to guarantee it charges to the 2.55v uvlo1 threshold before the out voltage exceeds the overvoltage threshold . step 6: determine r fb1 , r fb2 the feedback resistors , r fb1 and r fb2 , are chosen to regulate the overvoltage at 43 v. one way to quickly choose these resistors is to assign 100a or 1.2v across a 12.4k r fb1 . r fb2 would need to drop the remainder of the regu - lated voltage. dividing this remainder by 100a yields the value for r fb2 . in this example r fb2 drops 41.8v . when divided by 100a it results in a 422k value. step 7: determine c t , r1 during an overvoltage the power dissipated in the mosfet is dependent on the load current and the difference be - tween the supply and regulated voltages . it is necessary to keep the device power in a safe range . in the power mosfet data sheets there is a maximum safe operating curve displaying current versus drain to source voltage for a fixed pulsed time. other pulsed time data from dc to 10 s are plotted on the one graph. the different lines of operation generally follow a constant power squared ltc4366 436612fe for more information www.linear.com/ltc4366
19 applications information v dd sd r1 470k r2 100k out c g 2nf gate m1 ixth12n100l sd fb c t 3.3nf c1 0.47f r fb1 12.4k v out 0.5a (200v clamp) v in 160v (rectified 110v ac) 100v to 800v r fb2 2m 436612 f07 r ss 412k r g 10 r in 4.64m q1 bf722 ltc4366-2 timer base v ss danger! lethal voltages present figure 7. rectified 110v ac supply protected from 220v ac times time or p 2 t. knowing the power we then adjust the time using the timer capacitor to limit the p 2 t during overvoltage . in this example the mosfet data sheet has a 6400w 2 s p 2 t for a 10ms single pulse. in this application 250v minus 43v is applied across the mosfet at 3a. if the power is applied for less than 16.5ms then mosfet p 2 t limit is not exceeded: p = (250v C 43v) ? 3a = 621w p 2 t = (621w) 2 ? 16.5ms = 6363w 2 s prior to the moment when the output is regulated at 43v, the output is ramping from 28v to 43v. this ramp time is based on the 20a gate current charging the 10nf capaci- tor. using the equation for ramp time: ? t = c g ? ? v i g = 10nf ? 15v 20a = 7.5m s to be safe we set the overvoltage time to 10ms. we set the regulation time to be 2.5ms (the remainder of the 10ms overvoltage time minus the ramp time ). in this example it is assumed the 250 v overvoltage is a constant dc volt - age for 10ms. this duration exceeds mil-std- 1275 which specifies a 70s surge to 250v that decays in 1.6ms. us- ing the following equation (based on charging with 9a) to set the c t : c t = i t ? ? t ? v = 9a ? 2.5ms 2.8v 8.2n f in order to limit the sd pin current (10ma max) a collector resistor, r1, in series with q 1 is required . the maximum value for this resistor is around 5m. this requirement oc- curs when the pull-down is required to sink 1.6a from sd and v dd is clamped at 12v. high valued resistors are susceptible to leakage currents so we chose a 470 k resistor for r1. resistor r2 provides esd protection for q1s base. the gate resistor r g limits the parasitic trace capacitance on m1s gate node that could lead to parasitic mosfet self-oscillation. the recommended value for r g is 10. high voltage application in figure 7 the circuit accepts 110v ac (rectified to 160v) and protects the load from accidental connection to 220v ac by limiting the output to less than 200v. the circuit has a 100v to 800v v in operating range where the fet breakdown voltage limits the maximum input voltage . the c1 is set to 0.47f to provide a bypass for the charge pump that is large enough to provide good noise immunity from outside voltage transients. the timer capacitor is sized to give a 1 ms overvoltage regulation time that keeps the p 2 t below the 640w 2 s specified for this mosfet. ltc4366 436612fe for more information www.linear.com/ltc4366
20 28 v vehicle application the circuit in figure 8 adds reverse voltage protection to the standard 28v application shown in figure 6. there are three modes to this circuit : pass fet on when the input is 18v to 41v, clamping the output to 43v when more than 43v appears at the input and finally reverse voltage protection when up to C250v dc is present at the input. the reverse voltage protection consists of the circuitry inside the dotted box in figure 8. when a positive voltage is first applied to the input, d3 and the forward biased base-collector junction of q 2 allow the gate of m 2 to follow the input voltage minus a two diode drop . during this condition the body diode of m 2 is used to transmit power to the ltc4366. once the ltc4366 is powered up it fully enhances the gate of m 1 and m2 (via d 1). the m1 and m2 pass fets then provide a low impedance path to the load. in an overvoltage condition , d1 blocks excessive positive voltage from the input supply passing to the gate pin of the ltc4366. d4 eliminates current flow through r6 when the input is positive while d 3 prevents emitter base breakdown of q2 when the input is powering up. during negative input voltages q 2 turns on when current from r 6 (via d 4) develops a forward diode drop on r5. q2 then holds the gate of m 2 at the input voltage which turns m2 off. this blocks negative input voltages from reaching m1 and the load. d2 prevents damage to the ltc4366 s gate pin by clamping it at ground when the m2s gate is negative. low voltage application the circuit on the last page (surge protected automotive supply) starts up with minimum input voltage of 9v. in order to successfully start up at 9v and clamp the output voltage at 18v for input voltages up to 100v the value of r ss has to be small (1.91k). the fet used in this case has a 3 v threshold to ease the start-up requirements . the timer capacitor is sized to give a 2.5 ms overvoltage regulation time that keeps the p 2 t below the 420w 2 s specified for this mosfet. v dd sd r1 470k r4 270k r2 100k out c g 10nf gate m1 fqa62n25c m2 fdb33n25 reverse voltage protection sd fb c t 8.2nf c1 0.47f r fb1 12.4k v out 1.5a (43v clamp) v in 18v to 41v (250v dc) r fb2 422k 436612 f08 r ss 46.4k r g 10 r in 324k q1 mmbt3904 d4 bav3004w d3 bav3004w ltc4366-2 timer base v ss r5 470k q2 mmbt3904 r6 270k d2 bav3004w d1 bav3004w figure 8. 28v vehicle application with reverse voltage protection applications information ltc4366 436612fe for more information www.linear.com/ltc4366
21 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a) ltc4366 436612fe for more information www.linear.com/ltc4366
22 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.50 bsc ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) ltc4366 436612fe for more information www.linear.com/ltc4366
23 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . revision history rev date description page number a 1/12 added patents pending statement revised figure 4 in applications information section 1 11 b 2/12 removed reference to overcurrent faults under mosfet selection fixed orientation of m2 in figure 8 13 18 c 8/12 updated shutdown current from <20a to <14a changed mosfet part number and gate capacitor value used in the typical application added mp-grade order information and specifications added negative sign to graphs g12 x-axis and g18, g21 y-axis changed mosfet part number in figure 1 and figure 6 added section gate capacitor , c g changed i load current from 5a to 3a in design example updated c1 (max) values in step 5 calculations to 0.27f and worst case 0.49f updated calculated values in step 7, added supporting text changed mosfet part number and gate capacitor used in figure 7 1 1 2, 3, 4, 5 6, 7 11, 16 15 16 18 19 19 d 8/13 simplified diagram: corrected amplifiers input polarity in regulate diagram functional diagram: added switch in series with timer pull-down current 9 9 e 8/15 clarified ambient on operating temperature range; raised t jmax to 150c timer pin function: changed 278ms/f to 311ms/f figures 1, 6, 8: changed c t to 8.2nf from 10nf in c t equation, changed constant to 3.2 from 3.5; updated c t calculation 2 8 11, 16, 20 12, 19 ltc4366 436612fe for more information www.linear.com/ltc4366
24 ? linear technology corporation 2011 lt 0815 rev e ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4366 typical application surge protected automotive 12v supply v dd sd r1 470k r2 100k out c g 2nf gate m1 huf76639s3s sd fb c t 3.3nf c1 0.47f r fb1 12.4k v out 4a (18v clamp) v in 12v (9v to 100v) r fb2 169k 436612 ta02 r ss 1.91k r g 10 r in 29.4k q1 mmbt3904 ltc4366-2 timer base v ss related parts part number description comments ltc1696 overvoltage protection controller thinsot? package, 2.7v to 28v ltc2909 triple /dual inputs uv/ov negative monitor pin selectable input polarity allows negative and ov monitoring ltc2912/ltc2913 single/dual uv/ ov voltage monitor ads uv and ov trip values , 1.5% threshold accuracy ltc2914 quad uv/ov monitor for positive and negative supplies ltc3827/ltc3827-1 low i q , dual, synchronous controller 4v v in 36v , 0.8v v out 10v, 80a quiescent current ltc3835/ltc3835-1 low i q , synchronous step-down controller single channel ltc3827/ltc3827-1 lt3845 low i q , synchronous step-down controller 4v v in 60v , 1.23v v out 36v , 120a quiescent current LTC3850 dual, 550khz, 2-phase synchronous step-down controller dual 180 phased controllers, v in 4v to 24v , 97% duty cycle, 4mm 4mm qfn-28, ssop-28 packages ltc3890 low i q , dual 2-phase, synchronous step-down controller 4v v in 60v , 0.8v v out 24v, 50a quiescent current lt4256 positive 48v hot swap controller with open-circuit detect foldback current limiting, open-circuit and overcurrent fault output, up to 80v supply ltc4260 positive high voltage hot swap controller with 8-bit adc and i 2 c wide operating range 8.5v to 80v ltc4352 ideal mosfet oring diode external n-channel mosfets replace oring diodes , 0v to 18v ltc4354 negative voltage diode-or controller controls two n-channel mosfets , 1.2 s turn-off, C80v operation ltc4355 positive voltage diode-or controller controls two n-channel mosfets , 0.4 s turn-off , 80v operation lt4363 high voltage surge stopper 100 v overvoltage and overcurrent protection, latch-off and auto-retry options ltc4365 window passer C ov, uv and reverse supply protection controller 2.5v to 34v operation, protects 60v to C40v ltc4366 436612fe for more information www.linear.com/ltc4366

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